The present invention concerns multiple switch node power converters and, more particularly, to a method of and system for controlling the switching devices of multiple switch node power converters by modulating a single error voltage or current signal using only one of the modulation ramps at any given time.
Referring to FIGS. 1A, 1B, and 1C, a non-inverting, multiple switch node, four-switch buck-boost power converter 10 is shown. The buck-boost power converter 10 is structured and arranged to generate an output voltage, VO, that can be higher than, lower than, or equal to the input voltage, VIN. When the output voltage, VO, is greater than the input voltage VIN, the power converter 10 operates in boost mode 12, whereas when the input voltage, VIN, is greater than the output voltage, VO, the power converter 10 operates in buck mode 14. FIG. 1B and FIG. 1C show buck mode 14 and boost mode 12, respectively.
Conventionally, multiple switch node power converters 10 can be controlled to provide pure buck power conversion or to provide pure boost power conversion by adjusting or modulating the duty cycles, e.g., the ON and OFF pulse widths, of gate pulses to complementary switching devices disposed at each switch node. Switch node SW1, which includes complementary switching devices (“switches”) S1 and S2, and switch node SW2, which includes complementary switches S3 and S4, are disposed on either side of the inductor 15. During buck mode, complementary switches S1 and S2 at switch node SW1 become the “modulated” switches because their duty cycles or pulse widths are modulated as necessary, while switch S4 is a “nonmodulated” switch whose duty cycle is 100 percent or substantially 100 percent and switch S3 is a “nonmodulated” switch whose duty cycle is 0 percent or substantially 0 percent. Duty cycle for buck mode is defined as the ratio of the ON-time of switch S1 to the period of the entire switching cycle.
During buck mode, the voltage at the nonmodulated switch node SW2 is held constant, approximately equal to the output voltage, VO, while the voltage on switches S1 and S2 varies between approximately the input voltage, VIN, and ground. Referring to FIG. 1B, nonmodulated switch S3 is open (OFF) and nonmodulated switch S4 is closed (ON) during the entire switching cycle and the duty cycles or pulse widths of modulated complementary switches S1 and S2 are controlled to realize pure buck mode power conversion.
Conversely, during boost mode, complementary switches S3 and S4 at switch node SW2 become the “modulated” switches whose duty cycles or pulse widths are modulated as necessary. Switch S1 is the “nonmodulated” switch whose duty cycle is 100 percent or substantially 100 percent. Switch S2 is the “nonmodulated” switch whose duty cycle is 0 percent or substantially 0 percent. Duty cycle in boost mode is defined as the ratio of the ON-time of switch S3 to the period of the entire switching cycle.
In boost mode, the voltage at switch node SW1 is held constant, approximately equal to the input voltage, VIN, while the voltage on switches S3 and S4 varies between approximately the output line voltage, VO, and ground. Referring to FIG. 1C, with nonmodulated switch S2 open (OFF) and nonmodulated switch S1 closed (ON) during the entire switching cycle, the duty cycles or pulse widths of modulated complementary switches S3 and S4 can be controlled to realize pure boost mode power conversion.
During buck-boost mode, necessarily, all four switches S1-S4 are switched during the switching cycle. Ideally, two switches are always closed and two switches are always open during the switching cycle. During buck-boost mode, complementary switching pair S1 and S2 and complementary switching pair S3 and S4, however, are never simultaneously closed or simultaneously open.
Typically, the circuit operates in the buck-boost mode when the input voltage, VIN, and the output voltage, VO, are equal or substantially equal in magnitude. When this occurs and when switch S1 and switch S4 are closed simultaneously and/or when switch S2 and switch S3 are closed simultaneously, the voltage across the inductor 15 is zero or substantially zero. Thus, the inductor 15 is energized by the input voltage, VIN, which is to say, that the inductor current, iL, increases, only when switch S1 and switch S3 are closed and the inductor 15 is de-energized, which is to say that the inductor current, iL, decreases, only when switch S2 and switch S4 are closed.
Problematically, to reduce inductor current ripple—and, eventually, to reduce output voltage ripple—the overlapping ON duty cycle times of non-complementary switching pair S1 and S3 and of non-complementary switching pair S2 and S4 must be kept small while the inductor 15 is, respectively, energizing and de-energizing. Reducing inductor current ripple is desirable because, inter alia, it reduces associated ripple conduction power loss that is dissipated in the parasitic series resistances, e.g., due to switch ON-resistance, inductor ESR, and so forth, and it improves efficiency.
Referring to FIG. 2, the operation of a conventional multiple switch node, buck-boost power converter 20 will be described. At the output, the output voltage, VO, is sensed and scaled, VS, and fed back to an error amplifier 21. The sensed voltage, VS, is compared to a predetermined reference voltage, VREF, e.g., using the voltage error amplifier 21 or a transconductance amplifier. Based on the comparison, the voltage error amplifier 21 generates a voltage error signal, VERR, which is introduced as input into a pair of controllers 26 and 28. Optionally, the voltage error signal, VERR, can be reduced by the voltage corresponding to a sensed inductor current, iLRI, to generate a final voltage error signal, VERR-iLRI.
Those of ordinary skill in the art can appreciate that, alternatively, the error amplifier could be a current error amplifier that generates a current error signal to achieve the same results. For simplicity and not for purposes of limitation, the invention will be described using voltages rather than currents.
One controller 26, e.g., buck pulse width modulation (PWM) comparator (CBuck), compares the voltage error signal, VERR or VERR-iLRI, with a buck modulation/slope-compensation ramp VBuck. The other controller 28, e.g., boost pulse width modulation (PWM) comparator (CBoost), compares the voltage error signal, VERR or VERR-iLRI, with a boost modulation/slope-compensation ramp VBoost. Based on the results of the corresponding comparison, each of the PWM comparators 26 and 28 is adapted to generate gate-driving signals to gate drivers 23 and 27. The gate drivers 23 and 27 drive, i.e., turn ON or OFF, complementary switching pair S1 and S2 and complementary switching pair S3 and S4, respectively.
Referring to FIG. 3, a VBoost modulation ramp 32 is shown superimposed and level-shifted with respect to a VBuck modulation ramp 34. Ideally, for peak efficiency, the buck modulation ramp 34 and boost modulation ramp 32 should meet at plural points of intersection 39 without any overlap. If this ideal case ever occurs, the maximum buck duty cycle, i.e., at the acme 36 of the buck modulation ramp 34, extends to 100% or substantially 100%, and the minimum boost duty cycle, i.e., at the bottom 38 of the boost modulation ramp 32, is zero or substantially zero. In this ideal case, the power converter can operate in pure buck mode and in pure boost mode, but there is no transitional, buck-boost mode.
In practice, however, the ideal case rarely occurs. Indeed, due to circuit delays resulting from, for example, switching events, comparator delays, and the like, the ideal case generally does not occur. As a result, maximum and minimum duty cycles or pulse widths for the buck and boost modes never reach their ideal limits. Instead and as a result, a transitional, buck-boost mode occurs, which can be problematic.
Referring again to FIG. 3, a horizontal line corresponding to the direct current (DC) level 35 of the final voltage error signal, VERR-iLRI, is shown. As the input voltage, VIN, decreases, under the influence of the error amplifier and/or the current signal, iLRI, the DC level 35 of the final voltage error signal moves upwards from buck mode to boost mode. As the input voltage, VIN, increases, the DC level 35 of the final voltage error signal moves downwards from boost to buck mode. As the DC level 35 of the final voltage error signal moves from the very bottom 31 of the buck modulation ramp 34 to the very top 33 of the boost modulation ramp 32, the power converter 20 mode of operation changes from pure buck mode to pure boost mode. However, as the DC level 35 of the final voltage error signal transitions from near the acme 36 of buck modulation ramp 34 and near the bottom 38 of boost modulation ramp 32, the power converter 20 further transitions through an intermediate buck-boost mode.
For example, if, for the purpose of discussion, we assume that the demanded buck duty cycle required to satisfy the given VIN/VO ratio is 95% but that the power converter 20 can only deliver a maximum buck duty cycle of 90%, then the energy (power) supplied to the load 29 is less than what is needed to sustain the desired output voltage. In this case, remnant energy to make up the difference caused by the limited buck duty cycle must be provided by the effective boost converter, which is to say, that complementary switching pair S3 and S4, which for pure buck operation are, respectively open (OFF) and closed (ON) for the entire switching cycle, must be switched to generate the necessary remnant power. When complementary switching pair S3 and S4 and complementary switching pair S1 and S2 are both being switched, the power converter is in buck-boost mode.
Moreover, modulating the duty cycles or pulse widths of all four of the switches S1-S4 during the switching cycle can only be achieved when the DC level 35 of the voltage error signal intersects both the boost modulation ramp 32 and the buck modulation ramp 34 at their respective duty cycles. For this to occur, the buck modulation ramp 34 and the boost modulation ramp 32 must include some measure of overlap.
The minimum boost mode duty cycle is also limited. For example, for the purpose of discussion, if we assume that the required boost duty cycle is less than 5% but that the minimum achievable boost duty cycle is only 10%, as a result, even at its lowest possible duty cycle, i.e., 10%, switching of complementary switching pair S3 and S4 delivers surplus energy to the load 29.
The prior art has applied two steady-state solutions to this dilemma. The first involves sub-harmonic switching and the second involves increased ramp overlap. With sub-harmonic switching, ramp overlap stays as it is with complementary switching pair S1 and S2 being modulated at a duty cycle of, for example, 90%, and complementary switching pair S3 and S4 being modulated at a duty cycle of, for example, 10%. The output voltage charges and discharges in response to the surplus energy and energy shortage supplied to the load 29 during the various switching events.
Problematically, with subharmonic switching, the voltage error signal oscillates. Low frequency oscillation causes the DC level 35 of the final voltage error signal to intersect sometimes with just the boost modulation ramp 32, sometimes with just the buck modulation ramp 34, and sometimes with both ramps 32 and 34, such that the average value of the output voltage is in regulation. In terms of the switching activity, however, the system 20 is self-oscillating and the actual switching frequency, which is determined by the load 29, terminal voltages, ramp overlap, and filter values, is a subharmonic of the pre-established switching frequency.
Representative, measured waveforms for a 3-5.5V buck-boost power converter illustrating the above problem are shown in FIG. 4A and FIG. 4B. Referring to the bottom and middle waveforms in FIG. 4A and FIG. 4B, switch node SW1 (bottom waveforms), comprising complementary switching pair S1 and S2, is shown being modulated at approximately one-third of the clock frequency of 1.35 MHz, while switch node SW2 (middle waveforms), comprising complementary switching pair S3 and S4, is shown being modulated at approximately two-thirds of the clock frequency of 1.35 MHz. Other frequency combinations are observed depending upon voltage ratios and loading conditions.
The top waveforms show the resulting ripple 45 from each switching event. Thus, output voltage ripple is demonstrably increased at a frequency of approximately one-third of the clock frequency 1.35 MHz. Although not shown, the inductor current shows similar ripple effects, raising EMI concerns.
Alternatively, another possibility includes pre-defining an optimal operating condition for the power converter 20, which is to say, finding an operating condition at which the complementary switching pair S3 and S4 for boost mode is modulated at approximately 10%, while the complementary switching pair S1 and S2 for buck mode is purposely modulated at a lower duty cycle reduced from 90% (say 80% for discussion purposes). In this instance, the reduced energy resulting from modulation of complementary switching pair S1 and S2 can compensate for the surplus energy resulting from modulation of complementary switching pair S3 and S4.
Advantageously, because the net energy delivered to the output load 29 is equal to the demand, there is no subharmonic switching activity and, moreover, the voltage error signal remains stable. Problematically, to achieve this condition, as shown in FIG. 5A, the buck and boost modulation ramps 34 and 32 must be overlapped so that the DC level 35 of the error voltage signal intersects the buck modulation ramp 34 at the reduced 80% duty cycle level and the boost modulation ramp 32 at the prescribed 10% duty cycle level. This results in an increasing overlap 55. Indeed, in order for the optimal operating point to exist for all design conditions and to account for process/temperature variations, the overlap 55 between ramps 32 and 34 needs to be significantly increased.
As a result, as shown in FIG. 5B, when not at the optimal points of intersection, the power converter 20 will operate in the buck-boost mode 50 with the duty cycles of both complementary switching pairs S1 and S2 and S3 and S4 distant from their maximum and minimum values, respectively. As a result, higher current/voltage ripple and increased power loss can ensue. In addition, the relative positioning and overlap of the modulation ramps 32 and 34 need to be accurately controlled.
Accordingly it would be desirable to provide a method of and a system for controlling a multiple switch node power converter to modulate the duty cycles or pulse widths of complementary switching pairs without having to overlap the buck and boost modulation ramps and to avoid switching sub-harmonics.